Re: Question Regarding De-Skewing in Clause 48 (D2.0)
Hi :
If at state "BYTE_SLIP_WAIT" and next receive a good ||A|| column, it will
go to state "ALIGN_ACQUIRED_2" according to the current state machine
in D2.0, (should it go to state "ALIGN_ACQUIRED_1" in this case ??)
best regards
Steven Shen
Silicon Bridge Inc.
Rich Taborek wrote:
> Boaz,
>
> Answers below:
>
> Boaz Shahar wrote:
> >
> > Rich,
> > Something in "PCS de-skew state diagram" is not entirely understood:
> >
> > When the machine transients from "ALIGN_ACQUIRED_1" to "ALIGN_ACQUIRED_2" it
> > goes to the state "BYTE_SLIP_WAIT" where it waits for one additional byte to
> > be received.
> >
> > 1) What is the motivation? Is it to prevent a split ||A|| column to be
> > counted as two errors instead of just one?
>
> Yes. This is exactly the case.
>
> > 2) Why the machine does not transient through similar state while changing
> > states, for instance, from "ALIGN_ACQUIRED_2" to "ALIGN_ACQUIRED_3"
>
> It should. Don Alderrou of nSerial is submitting a comment to this
> effect.
>
> > Thx. for your help,
> > Boaz
>
> --
>
> Best Regards,
> Rich
>
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