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Question on XSBI Tx Timing.




All,

I have a question regarding the XSBI clock specifications in clause 51
of 802.3ae Draft 2.0.

Table 51-1, and text in subclause 51.3.1, state that both the XSBI
transmit and receive data are latched on the "rising" edge of their
respective clocks (PMA_TX_CLK<P> and PMA_RX_CLK<P>). Figures 51-5 and
51-7, which show the timing of the data capture on both the transmit and
receive interfaces, also show a data valid window centered on the
"rising" edge of the clocks.

However, figures 51-4, table 51-3, figure 51-6 and table 51-7 all show
the signals being launched with the data valid window centered on the
"falling" edge of the clocks and the data invalid period specified
around the rising edge. This appears inconsistent.

Any clarification as to what was intended here will be greatly
appreciated.

Thanks, & Best Regards,
Julio C. Hernandez
Texas Instruments
MSCL-Tustin California