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All,
Does the following 10GBase-W startup sequence look reasonable?
Regards,
Robin Uyeshiro
Adtech/Spirent
robin.uyeshiro@xxxxxxxxxxxxxx
10GBASE-W STARTUP
(View in Courier)
Initial state
>IDL> >LF> >??> >LF>
RS1 PCS1 WIS/PMA/PMD Fiber PMD/PMA/WIS PCS2 RS2
(OK) (!sync) (!sync) (OK)
<LF< <??< <LF< <IDL<
RS1 and RS2 go from OK to LF (2 TX_CLK cycles, 4 edges)
>RF> >LF> >??> >LF>
RS1 PCS1 WIS/PMA/PMD Fiber PMD/PMA/WIS PCS2 RS2
(LF) (!sync) (!sync) (LF)
<LF< <??< <LF< <RF<
PCS1 goes to sync and RF is clocked through PCS1 (Many + 5 TX_CLK cycles)
>RF> >RF> >??> >LF>
RS1 PCS1 WIS/PMA/PMD Fiber PMD/PMA/WIS PCS2 RS2
(LF) (sync) (!sync) (LF)
<LF< <LF< <LF< <RF<
RF gets clocked through to PCS2 (Many TX_CLK cycles)
>RF> >RF> >RF> >LF>
RS1 PCS1 WIS/PMA/PMD Fiber PMD/PMA/WIS PCS2 RS2
(LF) (sync) (!sync) (LF)
<LF< <LF< <LF< <RF<
PCS2 goes to sync and clocks RF through Tx & Rx (Many + 5 TX_CLK cycles)
>RF> >RF> >RF> >RF>
RS1 PCS1 WIS/PMA/PMD Fiber PMD/PMA/WIS PCS2 RS2
(LF) (sync) (sync) (LF)
<LF< <LF< <RF< <RF<
RS2 goes to RF and IDL passes through PCS2 TX (2 + 5 TX_CLK cycles)
>RF> >RF> >RF> >RF>
RS1 PCS1 WIS/PMA/PMD Fiber PMD/PMA/WIS PCS2 RS2
(LF) (sync) (sync) (RF)
<LF< <LF< <IDL< <IDL<
RF and IDL get clocked through to PCS1 (Many TX_CLK cycles)
>RF> >RF> >RF> >RF>
RS1 PCS1 WIS/PMA/PMD Fiber PMD/PMA/WIS PCS2 RS2
(LF) (sync) (sync) (RF)
<LF< <RF< <IDL< <IDL<
RF passes through PCS1 RX (3 TX_CLK cycles)
>RF> >RF> >RF> >RF>
RS1 PCS1 WIS/PMA/PMD Fiber PMD/PMA/WIS PCS2 RS2
(LF) (sync) (sync) (RF)
<RF< <IDL< <IDL< <IDL<
RS1 goes to RF (2 TX_CLK cycles)
>IDL> >RF> >RF> >RF>
RS1 PCS1 WIS/PMA/PMD Fiber PMD/PMA/WIS PCS2 RS2
(RF) (sync) (sync) (RF)
<IDL< <IDL< <IDL< <IDL<
IDL passes through PCS1 Tx (5 TX_CLK cycles)
>IDL> >IDL> >RF> >RF>
RS1 PCS1 WIS/PMA/PMD Fiber PMD/PMA/WIS PCS2 RS2
(RF) (sync) (sync) (RF)
<IDL< <IDL< <IDL< <IDL<
IDL passes through to PCS2 Rx, RS1 goes to OK (Many [> 59] TX_CLK cycles)
>IDL> >IDL> >IDL> >RF>
RS1 PCS1 WIS/PMA/PMD Fiber PMD/PMA/WIS PCS2 RS2
(OK) (sync) (sync) (RF)
<IDL< <IDL< <IDL< <IDL<
IDL passes through to RS2 Rx (3 TX_CLK cycles)
>IDL> >IDL> >IDL> >IDL>
RS1 PCS1 WIS/PMA/PMD Fiber PMD/PMA/WIS PCS2 RS2
(OK) (sync) (sync) (RF)
<IDL< <IDL< <IDL< <IDL<
RS2 goes to OK (64 TX_CLK cycles)
>IDL> >IDL> >IDL> >IDL>
RS1 PCS1 WIS/PMA/PMD Fiber PMD/PMA/WIS PCS2 RS2
(OK) (sync) (sync) (OK)
<IDL< <IDL< <IDL< <IDL<
The link is now up and ready for MAC traffic.
Assumptions:
Data takes 5 TX_CLK cycles (10 edges) to get through PCS in TX direction (?)
Data takes 3 TX_CLK cycles (6 edges) to get through PCS in RX direction (?)
RS takes 2 TX_CLK cycles (4 edges) to change to LF or RF state
RS takes 64 TX_CLK cycles (128 edges) to change to OK state
No errors are in data stream
No MAC packets are in data stream during startup
Everything starts at the same time and WIS framing has already sync'd
Abbreviations:
LF: Local Fault ordered set (4 bytes)
RF: Remote Fault ordered set (4 bytes)
IDL: 4 idle control bytes