RE: Clarification wanted: Draft 3.0 Figure 46-9 Link Fault Signaling State Machine
Ben,
I agree that a state machine showing the increment of the counter is
unnecessary, but I want to point out that the incrementing of the counter in
the current document is explicit in the definition of col_cnt and not
implicit.
The col_cnt definition says explicitly: "This counter increments at RX_CLK
rate (on both the rising and falling clock transitions) unless reset."
This is the way most watchdog 802.3 counters and timers work. A little state
machine to count columns wouldn't be any clearer and wouldn't enhance
understandability of the state machines.
Regards,
Pat
-----Original Message-----
From: Ben Brown [mailto:bbrown@xxxxxxxx]
Sent: Friday, May 04, 2001 6:34 PM
To: Daniel Koehler
Cc: stds-802-3-hssg@xxxxxxxx
Subject: Re: Clarification wanted: Draft 3.0 Figure 46-9 Link Fault
Signaling State Machine
Daniel,
The definition of col_cnt in 46.3.4 on page 255 implies that
col_cnt increments with both edges of RX_CLK unless it is
reset. Explicit increment is unnecessary.
Ben
Daniel Koehler wrote:
>
> Hello,
>
> by inspecting Figure 46-9 in draft D3.0 on page 256 we see the following
> implementation problems.
>
> The States "COUNT" and "FAULT" reset the counter col_cnt to zero.
> But col_cnt is never incremented in any state, so the exit of these states
> based on col_cnt > 127 will never be reached.
>
> Is there some implicit meanins we just missed, or is the diagram not
correct ?
>
> Another question: Is there a Jitter Spec on the XGMII TX/RX clocks ?
>
> Regards,
>
> Daniel
>
> --
> Daniel Koehler, dkoehler@xxxxxxxxxxxxxx
> MorethanIP GmbH
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