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Folks -
Per John D'Ambrosia's work on EMI and crosstalk
testing for XAUI, it was recommended that CJPAT be modified to avoid
transmitting synchronous patterns in all 4 lanes. I present 2 options for
resolving this below.
OPTION 1: This option keeps the present CJPAT core in lanes 1 and 3, EXCEPT that they attempt to run with opposing disparity from each other due to an inserted disparity flipper in the first byte in lane 3 (an inserted byte in lane 1 does not flip disparity). I say "attempt" because (relative) starting disparities can never be assured. The 2 cores will be opposing only if disparities coming into the start of the pattern are the same, AND there is nothing transmitted between repetitions of the pattern that subsequently shifts their relative disparity. Note - if starting disparities are not controlled to match as hoped, the disparity bytes causes the 2 lanes to revert to synchronous transmission. Lanes 1 and 3 begin with low transition density then switch to high
transition density. For option 1, this order is reversed in lanes 2 and 4 -
lanes 2 and 4 begin with high transition density then switch to low transition
density. Therefore, lane pairs 1-3 and 2-4 will not be synchronous, regardless
of disparities. Opposing disparity is also attempted between lanes 2 and 4 with
a disparity flipper in lane 4.
Note that CJPAT's per-lane jitter properties require specific starting
disparity in each. Since starting disparities cannot be assured, CJPAT was
designed so that all lanes switch their disparities 1/2 way through the pattern,
otherwise repeating the first half. Half of each lane's pattern will have the
appropriate jitter properties; the other half will not (but will still provide
useful "randomization". This characteristic of CJPAT has not changed with
proposed Option 1.
4x data # of
row repeats
D5 55 07 07 1 disparity
control
7E B5 7E B5 40 7E EB 7E EB 1 7E F4 7E F4 1 7E EB 7E EB 1 7E F4 7E F4 1 7E EB 7E EB 1 7E F4 7E F4 1 7E EB 7E EB 1 7E F4 7E F4 1 7E 7E 7E 7E 84 F4 7E F4 7E 1 EB 7E EB 7E 1 F4 7E F4 7E 1 EB 7E EB 7E 1 F4 7E F4 7E 1 EB 7E EB 7E 1 F4 7E F4 7E 1 AB 7E AB 7E 1 B5 7E B5 7E 40 EB F4 EB F4 1 F4 EB F4 EB 1 EB F4 EB F4 1 F4 EB F4 EB 1 EB F4 EB F4 1 F4 EB F4 EB 1 EB F4 EB F4 1 F4 AB F4 AB 1 7E B5 7E B5 40 start 2nd half of pattern 7E EB 7E EB 1 7E F4 7E F4 1 7E EB 7E EB 1 7E F4 7E F4 1 7E EB 7E EB 1 7E F4 7E F4 1 7E EB 7E EB 1 7E F4 7E F4 1 7E 7E 7E 7E 84 F4 7E F4 7E 1 EB 7E EB 7E 1 F4 7E F4 7E 1 EB 7E EB 7E 1 F4 7E F4 7E 1 EB 7E EB 7E 1 F4 7E F4 7E 1 AB 7E AB 7E 1 B5 7E B5 7E 40 EB F4 EB F4 1 F4 EB F4 EB 1 EB F4 EB F4 1 F4 EB F4 EB 1 EB F4 EB F4 1 F4 EB F4 EB 1 EB F4 EB F4 1 F4 AB F4 AB 1 F7 C6 DB D2 1 CRC OPTION 2: Option 2 is ~1/2 the length of option 1. This is accomplished by selecting disparity flipping bytes and resulting CRC in a manner that returns the opposite starting disparities to the beginning of the pattern. Each time the pattern runs, each lane alternates disparity so that like option 1, half the time each lane achieves the desired jitter properties, and the other half of the time it does not. Note that this assumes that the pattern repeats with an odd number of IPG
rows as shown in 802.3ae draft 3.3 (12 bytes). If the length of the IPG is
continually an even number of rows, then the disparity will not flip, and the
pattern could get "stuck" with either the correct of incorrect jitter
properties.
Again, lanes 2 and 4 reverse the sequence of high and low transition
density with lanes 1 and 3. Also like option 1, lanes 1 and 3 attempt relative
opposing disparity, and lanes 2 and 4 attempt relative opposing disparity.
4x data # of
row repeats
55 55 13 07 1 disparity
control
7E B5 7E B5 40 7E EB 7E EB 1 7E F4 7E F4 1 7E EB 7E EB 1 7E F4 7E F4 1 7E EB 7E EB 1 7E F4 7E F4 1 7E EB 7E EB 1 7E F4 7E F4 1 7E 7E 7E 7E 84 F4 7E F4 7E 1 EB 7E EB 7E 1 F4 7E F4 7E 1 EB 7E EB 7E 1 F4 7E F4 7E 1 EB 7E EB 7E 1 F4 7E F4 7E 1 AB 7E AB 7E 1 B5 7E B5 7E 40 EB F4 EB F4 1 F4 EB F4 EB 1 EB F4 EB F4 1 F4 EB F4 EB 1 EB F4 EB F4 1 F4 EB F4 EB 1 EB F4 EB F4 1 F4 AB F4 AB 1 E6 42 BC 62 1 CRC In both options 1 and 2, START/PREAMBLE/SFD and IPG remain identical to what are shown in 802.3ae D3.3. ALL data here is consistently shown in little endian format. Many thanks to Ben Brown of AMCC for developing a CRC algorithm for this
work.
Comments? Tom Lindsay
Stratos 425/672-8035 x105 |