RE: [802.3ae] A question about D3.4/ 47, 48
OK, Thx.,
Anyway, it should be mentioned some where in the Standard. Because according
to current definition, the mask describes only Amplitude, not phase.
Boaz
> -----Original Message-----
> From: Howard A. Baumer [mailto:hbaumer@xxxxxxxxxxxx]
> Sent: Thursday, November 29, 2001 7:43 PM
> To: Boaz Shahar
> Cc: 'rtaborek@xxxxxxxxxxxxx'; HSSG (E-mail); Eyran Lida
> Subject: Re: [802.3ae] A question about D3.4/ 47, 48
>
>
> Boaz,
> Once the data is transmitted it is not going to pick up
> sinusodial
> jitter, it will only pick up noise which is high frequency
> jitter. The
> sinusiodal jitter comes from the clock source generating the data.
> Since it is assumed that all four lanes, 0-3, are derived
> from the same
> clock source they will have the same sinusiodal jitter. Thier phase
> might be different by the skew in the channel, their instantaneous
> frequency difference due to low frequency sinusiodal jitter
> will be the
> same. Therefore, the 8.5UI of 22KHz sinusiodal jitter doesn't figure
> into the deskew budget.
> Also the specified skew that the deskew circuits has to
> handle is 41UI
> but the amount of skew allowed by the ||A|| placement is
> 80UI, so there
> is lots of margin in the skew budgets.
>
> Howard Baumer
>
> Boaz Shahar wrote:
> >
> > Rich,
> >
> > > -----Original Message-----
> > > From: Rich Taborek [mailto:rtaborek@xxxxxxxxxxxxx]
> > > Sent: Thursday, November 29, 2001 2:03 PM
> > > Cc: HSSG (E-mail)
> > > Subject: Re: [802.3ae] A Questuin about D3.4/ 47, 48
> > >
> > >
> > >
> > > Boaz,
> > >
> > > Please review the jitter tolerance mask explanatory material
> > > in Annex G
> > > of the Fibre Channel - Methodology for Jitter Specification.
> > > Here's the
> > > link to that document:
> > > ftp://ftp.t11.org/t11/member/fc/jitter_meth/99-151v2.pdf
> >
> > In FC-MJS page 28 Figure 9, the max value for the amplitude of the
> > sinusoidal jitter is 1.5 UI. Note that the mask defines
> only the amplitude,
> > and not the phase of the jitter. When the phase of the
> Sinusoidal jitter
> > applied to a lane is exactly the opposite phase of the
> sinusoidal jitter
> > applied to another lane, the peak-to-peak jitter is
> translated to skew
> > between those two lanes, when the frequency of the jitter is low.
> >
> > (BTW, being accurate here, the MJS mask do not define the jitter in
> > [0,42Khz])
> >
> > However, while 1.5 UI is not too big, and can be absorbed
> or represented by
> > the line "PMA Rx" in the skew budget table D3.4/table 48-5,
> the value of
> > additional 8.5 UI skew is quite big and should be expressed
> there some how.
> >
> > >
> > > All relatively low frequencies, jitter orders of magnitude
> > > above 22 kHz
> > > is completely tracked out by the CDR unit associated with a XAUI
> > > receiver on each lane independently.
> >
> > This is exactly the reason that peak-to-peak sinusoidal
> jitter amplitude
> > generates a skew between lanes. Each of the CDRs tracking them
> > independently, and if Jitter applied with 180 degree phase
> shift, you get a
> > skew of 8.5 UI, as each of the CDRs take its lane to th
> eopposite direction.
> >
> > Boaz
> >
> > >
> > > Best Regards,
> > > Rich
> > >
> > > --
> > >
> > > Boaz Shahar wrote:
> > > >
> > > > Rich,
> > > > I do not think it has something to do with the 100ppm
> > > drift. Drift is
> > > > frequency deviation between two different clock domains,
> > > while jitter is the
> > > > deviation of a certain signal edge location from its
> > > nominal location,
> > > > regardless its frequency or other clock domain frequency.
> > > >
> > > > I think that the interpretation of jitter is that
> > > Jitter=The deviation of a
> > > > certain bit edge from its nominal location. So, saying
> > > Jitter of 8.5 UI in
> > > > frequency 0 is allowed, as in figure 47-5, is saying that a
> > > certain point
> > > > may be misslocated by 8.5 UI. This can happen even with DRIFT=0.
> > > >
> > > > For instance, suppose there is no skew at all, but lane 0
> > > is jittering to
> > > > the right by 4 bits, and lane 1 to the left by 4.5 bits,
> > > and this happens in
> > > > jitter frequency=0, that is, in a very slow way. This
> > > implies that this
> > > > situation is almost constant. So there is is a skew of 8.5
> > > bits between lane
> > > > 0 and lane 1 although if there was not any jitter, the skew
> > > would be 0.
> > > >
> > > > Otherwise, can somebody explain the meaning of the
> > > Sinusoidal jitter mask in
> > > > figure 47-5? What is happening there in the interval [0,22Khz]?
> > > >
> > > > Boaz
> > > >
> > > > > -----Original Message-----
> > > > > From: Rich Taborek [mailto:rtaborek@xxxxxxxxxxxxx]
> > > > > Sent: Thursday, November 29, 2001 3:46 AM
> > > > > To: Boaz Shahar
> > > > > Cc: HSSG (E-mail)
> > > > > Subject: Re: [802.3ae] A Questuin about D3.4/ 47, 48
> > > > >
> > > > >
> > > > > What??? 8B/10B has a max run length of 5. This translates
> > > to a lowest
> > > > > frequency component of 312.5 MHz. This is slightly higher
> > > > > than 22 KHz.
> > > > >
> > > > > The "slanted" portion of Figure 47-5 is the low
> frequency mask and
> > > > > corresponds to the +/-100 ppm XAUI clock tolerance. At
> > > the really low
> > > > > frequencies, I believe that the 8.5 UI corresponds to the
> > > > > number of bits
> > > > > that would have to be buffered in the case that clock
> tolerance
> > > > > compensation is performed for a packet length equivalent to
> > > > > 22 kHz. The
> > > > > 8.5 UI and the slanted line itself has no relevance if
> > > clock tolerance
> > > > > compensation is not performed. The 8.5 UI is only relevant on
> > > > > a per lane
> > > > > basis and has no significance lane to lane. Therefore, the 41
> > > > > bit deskew
> > > > > in Table 48-5 holds.
> > > > >
> > > > > Best Regards,
> > > > > Rich
> > > > >
> > > > > --
> > > > >
> > > > > Boaz Shahar wrote:
> > > > > >
> > > > > > In clause 47, 47.3.4.6 and figure 47-5, the sinusoidal
> > > > > jitter is 8.5 UI in
> > > > > > very low frequency (Interval [0,22Khz]). This means that
> > > > > there is additional
> > > > > > skew of 8.5 UI between lanes in the XAUI. That is included
> > > > > in Table 48-5
> > > > > > (Skew Budget)? In other words, while doing de-skewing, one
> > > > > should consider
> > > > > > 41+8.5 as the max deskew situation or just 41?
> > > > > > Thx.,
> > > > > > Boaz
> > >
> > > ---------------------------------------------------------
> > > Richard Taborek Sr. Intel Corporation
> > > XAUI Sherpa Intel Communications Group
> > > 3101 Jay Street, Suite 110 Optical Group Marketing
> > > Santa Clara, CA 95054 Santa Clara Design Center
> > > 408-496-3423 JAY1-101
> > > Cell: 408-832-3957 mailto:rich.taborek@xxxxxxxxx
> > > Fax: 408-486-9783 http://www.intel.com
> > >
>