ITU-T G.957 CID pattern
This is a repeat of information in my email "Notes from serial PMD call of
16 Jan. 01" sent Thu 18 Jan 2001 20:15 GMT, which the email archiver didn't
capture.
WAN jitter test patterns
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I reported some more detail I had found on the ITU-T G.957 CID pattern.
Here is an expanded version:
The pattern is defined in informative appendices to G.958 (11/94) and the
currently prepublished G.957. They seem to agree.
[CID]=[A][B][D][C][B][D][A]..
A = all ones 9 bytes long
B = PRBS 7 with mark density of 1/2
C = all zeros 9 bytes long
D = a data block consisting of the first row of section overhead bytes for
the STM-N system under test. In other words A1..n, A2..n, C1..n/3,
10101010..2n/3 where n = 48 or 192. Our "C1..n" are defined in the WIS
clause as J0, Z0..n-1 where 50.3.2.3 says Z0 = 11001100. A1, A2 are not
spelt out but referred to in clause 50; G.707 has A1 = 11110110, A2 =
00101000.
The recommended length for B in G.958 is ideally 10,000 bits with a minimum
recommendation of 2,000 bits, however this is not clearly defined and the
duration should be longer than the longest time constant in the clock
recovery system.
The PRBS 7 is defined in (formerly) G.709, (now) G.707. G.707 (3/96) has
1+X^6+X^7. This is also in the WIS clause 50.3.3 and figure 50-3.
G.958 recommends that the scrambler free runs so that all possible sequences
follow the block of ones and zeros, but recognises that this may be
impractical. Or suggests use fixed worst case phase of PRBS, "for further
study".
The test is seen as a design or subassembly thing rather than a general
acceptance test.
By the way, CID patterns (several options) are implemented in product E4544A
which goes with Agilent BERTs.
Piers