Re: SJTP: Minutes from today's call
Tom Alexander wrote:
> Ben (and others),
> <snip>
>
> Further:
> - the WAN-PHY has a bypass mode specified, whereby the output of the 64B/66B PCS can be directly passed to the XSBI;
> - therefore, if a common test pattern can be created and specified in Clause 49, and allowed to be operative in both
> LAN-PHY and WAN-PHY (bypass) modes, no further changes to the spec are needed;
The WIS bypass allows the PCS connection directly to the PMA. However, if only 10GBASE-W
port types can be supported this bit is in-active. Therefore the proposed solution will
not work for all cases.
A possible work-around is to change the functionality associated with the bypass.
It should be possible to connect the PCS directly to a 10GBASE-W port type if
the data rate from the PCS was limited to 9.95328Gbps. Can the PCS support this
additional data rate for jitter test pattern generation?
Related to this, when jitter test pattern mode is used in a system operating
with a WIS and an ELTE, I am assuming that the ELTE would terminate
the jitter test pattern and not forward this to the far-end ethernet port.
Is this correct?
--
Tim Warland P.Eng.
Hardware Design Engineer Broadband Products
High Performance Optical Component Solutions
Nortel Networks (613)765-6634