Re: WIS jitter test pattern generator and checker - current definition

["Tim Warland" <twarland@xxxxxxxxxxxxxxxxxx>]

Tom Alexander wrote:

All,

As promised at the last meeting, here are the current definitions of the WIS
jitter test pattern generator and checker functions. I'm including a PDF extract <snip>

Tom, I can't read JTPATpagesfromcls50.2tosendtopeople.pdf.

All:

I have thrown together a proposal for the pattern generator within the
WIS block. This should be viewed as preliminary, perhaps it could be
used as a baseline moving forward.

To summarize this document, the "pattern" is two SONET frames in length.
Each frame has a CID pattern in the Z0 bytes immediately preceding the
start of the payload. The objective of this alignment is that any resultant
eye closure or Rx PLL loss of lock would be detected in the payload portion
not the overhead - so the WIS doesn't have to process Z0 bytes. The
CID would alternate from all zero's first frame to all one's in the second.

The payload is generated by a 2^23-1 PRBS which would be loaded
with seed A and seed A invert (to keep the disparity low). The PRBS
would start at a known reset value and run for a single SONET frame
from seed A, then a single SONET frame from seed A invert. It is
my feeling that the reset point for the PRBS should be aligned to the
start of the SPE (i.e immediately after the J1 byte in the POH).
Note that since 10GE has a    synchronous payload (fixed value
for H1H2) the value of each byte in the frame can be determined
in advance. The seed should be chosen to work with the CID
alignment. Note that the output of the PRBS still passes through
the SONET scrambler.

For reception, the WIS would operate as it does now. Overhead
is processed as defined by Clause 50 with the data within the
SPE forwarded to the PRBS for BERT accumulation. For external
bit based pattern BERTs, this tester could be programmed
with every value in the 2 frames (2.5Mbits which is within reason
for equipment vendors) including the CID (which the WIS
doesn't specifically test).  For SONET based BERTs, they
extract the SPE from the frame. These devices (as they are
currently designed) would detect an error at every reset point
(once per frame). A work around would have to be developed
by these equipment vendors.

Please provide your feedback. I don't think I'll discuss this at
this weeks SJTP ad hoc telecon. We should set a target to
be ready next week (June 12).

-- 
Tim Warland     P.Eng.
Hardware Design Engineer  Broadband Products
High Performance Optical Component Solutions
Nortel Networks                (613)765-6634

Clause_50A2.pdf