| Thread Links | Date Links | ||||
|---|---|---|---|---|---|
| Thread Prev | Thread Next | Thread Index | Date Prev | Date Next | Date Index |
|
I support keeping the bj end-to-end budget while leaving the opportunity to repartition. Vineet – the short answer is that a Server may also need a long host channel, and since it is cheap PCB, it is more dB loss/inch that what is generally used
in a switch. Verbose answer: ·
On the server, the Ethernet NIC is sometimes delivered on an add-in card, sometimes directly on the mother board. ·
When on an add-in card, the NIC’s PHY can
usually be placed within a couple inches of the MDI. No problem. ·
Lowest cost, highest attach generally happens when the NIC function is on the motherboard, so that’s kind of the end goal. (The 25G CFI was strongly
based upon low cost.) ·
When the NIC is on the motherboard, the host trace may need to be much longer, up to 6-8” due to placement constraints.
o
Ethernet (at least the high-speed serial flavors) is generally the highest speed interface on the server, BUT low priority for placement & floor planning.
·
Server motherboards are still built with low cost PCB material. PCIe & DRAM interfaces do not require Nelco-13 or Meg6. (If a server guy says he
is using “mid-loss” material, that is not the same definition you use… ask what the Df/Dk is.
J) ·
Result: Server board IL is ~2-3dB/inch @12.7GHz ·
CR4 host budget is ~6.25db. ·
Server (with current material) needs about 12dB for reasonable layout flexibility… geez we’d take 20 if you gave it to us… ·
Going to low loss material that would support 6” reach would more than double the cost of the mother board.
·
In rough terms, the NIC component cost is <<10% of a server cost (can range from 1% to 10% depending on speed (1G/10G/25G/40G) & number of ports,
etc.). it’s roughly on par with the cost of the motherboard PCB itself. ·
Thus if you double the PCB cost, you are doubling the cost of supporting Ethernet on the server.… at least ·
… all for the sake of having 5m reach, which is a fringe tail of the cable distribution. Most Server-TOR (truly “TOR”) links are <3m)
Our rules prevent a more detailed description of the cost, and there are so many variables that being more precise would not be more accurate. I propose that a 3m reach would yield the lower system cost for the majority of systems. Longer reach needs can use SR, AOC, BASE-T… From: Vineet Salunke (vineets) [mailto:vineets@xxxxxxxxx]
Matt, I agree, staying with CR4 specs would be best, but I am trying to understand the need for larger host loss. The main volume would be “SFP” ports used on both switch and server, so we should optimize for that. QSFP switch ports will not be able to use the larger loss, but can still provide 4x25G CR breakout. --vineet From: Matt Brown (APM) [mailto:mbrown@xxxxxxx]
Hi Vineet, I think it makes a lot of sense to retain the 802.3bj host loss. The case in point would be a switch with 4x25G connectors that may be used for either a signal
100G Ethernet port (100GBASE-CR4 per 802.3bj) or four 25G Ethernet ports (25GBASE-CR per new 25G project). From: Vineet Salunke (vineets) [mailto:vineets@xxxxxxxxx]
Chris, We heard on the call yesterday, at least 3 demands that do not exactly match Clause 92. ·
Need to reduce the host loss on the server side, to reduce total loss and avoid use of FEC. ·
Need to further optimize around 3m cables for above. ·
And I also heard need to allow larger host loss for the TOR switch side (when using RS-FEC). So can we avoid the direct reference to Clause 92 specifications ? --vineet From: Christopher T. Diminico [mailto:00000025925d7602-dmarc-request@xxxxxxxx]
Rich,
Hopefully this addresses both you and George.
Given the intent is to operate over channels consistent with the channel (TP0-TP5) specified in IEEEStd802.3bj-2014 Clause92.
•Define a single-lane 25Gb/s PHY for operation over channels consistent with the channel specified in IEEEStd802.3bj-2014 Clause92 (Fig 92-2 - TP0-TP5) Regards, Chris DiMinico
-----Original Message----- Both suggestions allude to a specific host/module budget which I believe needs to re-evaluated in task force. Perhaps: Define a single-lane 25Gb/s PHY for operation over copper twin-axial cables, host channels, and module channels consistent with channels (TP0-TP5) specified
in IEEEStd802.3bj-2014 Clause93 This sort of reinforces a single silicon solution. From: George Zimmerman [mailto:george@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx]
Chris – Clause 92 has a lot of non-channel stuff in it, and the parenthetical insert, while clarifying to those who know clause 92 intimately, isn’t perhaps as clear as
you could be. Pointing to the correct subclause, a figure or a table would be a lot better. The wording itself leads to confusion because it says “over copper twinaxial cables consistent with”, but TP0 to TP5 includes more than the twinax cables, as you
know. We end up with a couple of choices: 1) Just identify the cables in clause 92, or 2) Say operate over the whole TP0 to TP5 channel in clause 92 (I apologize because I have another call which conflicted with yesterday’s meeting – I don’t have an opinion on whether using the whole channel from TP0 to TP5
is in fact the correct objective, or whether you want to do just the cables) If you just want to do (1) just the cables, the cable assembly is specified in 92.10 (and references elsewhere), I would suggest stating •Define a single-lane 25Gb/s PHY for operation over copper twin-axial cables consistent with cable assemblies specified in IEEEStd802.3bj-2014 Clause92.10 And, if you want to do the whole channel, including the PCB, as you stated, from TP0 to TP5, Clause 92.9 clearly specifies this (by referencing other subclauses) •Define a single-lane 25Gb/s PHY for operation over copper twin-axial cables consistent with cable assemblies specified in IEEEStd802.3bj-2014 Clause92.9 Note I’m looking at draft 3.2 of the 802.3bj, and don’t have the final published version. George Zimmerman Principal, CME Consulting Experts in Advanced PHYsical Communications Technology 310-920-3860 (PLEASE NOTE NEW EMAIL ADDRESS. THE OTHER WILL STILL WORK, BUT PLEASE USE THIS FOR CME BUSINESS) From: Christopher T. Diminico [mailto:00000025925d7602-dmarc-request@xxxxxxxx]
Colleagues,
Based on the discussions of the objective given on slide 9 second bullet in
http://www.ieee802.org/3/25GSG/public/adhoc/architecture/nowell_081214_25GE_adhoc.pdf
during the ad-hoc yesterday, I suggest we explicitly identify 802.3bj channel by adding (TP0-TP5).
Change from •Define a single-lane 25Gb/s PHY for operation over copper twin-axial cables consistent with channels specified in IEEEStd802.3bj-2014 Clause92 To •Define a single-lane 25Gb/s PHY for operation over copper twin-axial cables consistent with channels (TP0-TP5) specified in IEEEStd802.3bj-2014 Clause92 Regards,
Chris DiMinico -----Original Message----- Sorry everyone – calendar screw up on my side around the re-arranged architecture ad-hoc meeting. Will update soon with improved logistics. Mark On 8/19/14, 5:42 PM, "Mark Nowell (mnowell)" <mnowell@xxxxxxxxx> wrote: Dear 25Gb/s Ethernet Study Group Members, A few reminders and updates: 1)
Optical Ad-hoc is tomorrow Wed 8/20 @ 9am PST. Dial in details are here: http://www.ieee802.org/3/25GSG/public/adhoc/index.html 2)
Architecture ad-hoc meeting next week has moved to Wed 8/27 @ (am PST (shifted from Tues). Dial in details are here: http://www.ieee802.org/3/25GSG/public/adhoc/index.html 3)
Reminders on Call for presentations and September Meeting planning. Presentation request deadline is Friday Aug 29th. Please see my original email for details on meeting logistics and travel planning (We meet all-day Thurs and Friday). http://www.ieee802.org/3/25GSG/email/msg00004.html As a reminder, the September Study Group meeting has limited meeting time and the presentations will be focused on the Study Group work of building objectives,
developing responses to the CSD (5 Criteria) and PAR. Presentations outside of the scope of those priorities will be given time on agenda as possible. Regards…Mark |