Re: [STDS-802-3-400G] one comment about 4x100G breakout RE: IEEE P802.3

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Thanks,

Ali Ghiasi

Ghiasi Quantum LLC

On Jun 24, 2015, at 2:57 PM, Kolesar, Paul <PKOLESAR@xxxxxxxxxxxxx> wrote:

Ali,
Thanks for trying to clarify, but I’m still not understanding your assertions which make it sound like 25G is pointless because 50G is in development.

The reason 25 GbE exist is because it come for free practically out of a 4x25G SerDes core, as Brad said and press announcement from Broadcom and Mellanox have stated 50 GbE based on 2 lane also exist now. When SerDes I/O speed moves from 25G/lane to 50G/lane then we can get 50 GbE with small premium over 25 GbE, this is why many of us are pushing to start the 50 GbE project sooner than later so the standardization process happens in IEEE instead of MSA that IEEE has to deal with later on.

Don’t take me wrong. I am not disputing that rates will continue to climb. But with the advent of smaller generational rate increases (i.e. 2x instead of 10x), the overlap of generations of equipment in volume production is inevitable. This will give rise to a greater variety of switch configurations sporting various rate interfaces. In support of this trend we are already seeing announcements of chips with configurable rates running from 10G to 25G to 40G to 100G.

I agree, but configuring a 100G as 10 G port ends of to be a very expensive 10G port!

If the 400G-SR16 transceiver offers cost savings compared to implementations using 16 individual 25G transceivers, and ToR switches are high volume items (which they are), it seems to make sense to wring cost out of the switch by revising the layout to replace the 16 transceivers with a single device. Since 25G silicon is available now, there need be no delay of 1 or 2 generations for 400G-SR16 to be deployed on ToR switches. Such a switch could be made non-blocking by also applying the same 400G-SR16 to its uplinks. Or it could deliver low blocking ratios with the same building blocks by supporting increased numbers of server ports (e.g. 32, 48, …).

What you say would make sense if someone was implementing 400 GbE on TOR now, by the time 400GbE gets into TOR boxes the signaling will be 50G/lane.

There is a market for SR4/SR12/SR16 based on 25G/lane now that is connecting large fabric between shelf/chassis, obviously the other one is HPC applications. I don’t expect you are going to get rich selling SR16 into Ethernet front panel ports, but there should be enough intra-system applications to make it a worthwhile development for the supply base.

Regards,
Paul

From: Ali Ghiasi [mailto:aghiasi@xxxxxxxxx]
Sent: Wednesday, June 24, 2015 3:28 PM
To: Kolesar, Paul
Cc: STDS-802-3-400G@xxxxxxxxxxxxxxxxx
Subject: Re: [STDS-802-3-400G] one comment about 4x100G breakout RE: IEEE P802.3bs 400 Gb/s Ethernet Task Force Logic Ad Hoc

Paul

I said by "the time server and silicon technology catches where 400 GbE is integrated on the TOR”! In 1-2 silicon generation when 400 GbE is integrated on the TOR then you will also see 50 GbE on the server.

We are developing 25GbE because 10G is not sufficient for a segment of market and 25 GbE cost less than the alternative the 40 GbE. The same economic will apply to 50 GbE later on!

Thanks,
Ali Ghiasi
Ghiasi Quantum LLC

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On Jun 24, 2015, at 12:31 PM, Kolesar, Paul <PKOLESAR@xxxxxxxxxxxxx> wrote:

Ali,
In order for 50G lanes to make sense for ToR switches, servers must be able to use that rate. I think the market will put 25G servers to several years of use before 50G servers overtake them. Witness the time lag for 10G servers to overtake sub-10G servers. 10G is now in its prime with 25G up and coming. If this is not true, why are we bothering to develop 25GE?

Paul

From: Ali Ghiasi [mailto:aghiasi@xxxxxxxxx]
Sent: Wednesday, June 24, 2015 1:59 PM
To: Kolesar, Paul
Cc: STDS-802-3-400G@xxxxxxxxxxxxxxxxx
Subject: Re: [STDS-802-3-400G] one comment about 4x100G breakout RE: IEEE P802.3bs 400 Gb/s Ethernet Task Force Logic Ad Hoc

Paul

Initial application of 400 GbE will follow 100 GbE early deployment SMF ports on Routers and Spin switches. Du Wenhua statement is correct to say 400 GbE will not be integrated initially on TOR. By the time server and silicon technology catches where 400 GbE will be integrated on TOR then we will have 50 GbE on single lane of SMF/MMF.

So 16x25G MMF has limited life/application and soon to be obsolete with emergence of 50G eco-system.

Thanks,
Ali Ghiasi
Ghiasi Quantum LLC

<image001.png>

On Jun 24, 2015, at 7:25 AM, Kolesar, Paul <PKOLESAR@xxxxxxxxxxxxx> wrote:

Du Wenhua,
I thanks for your thoughts. This is a valuable discussion.

I do not disagree with your points on KP4 and KR4 FEC at 100G, but I have a different view on your conclusion point 3). I think 16x25G and 8x50G break-outs can play a role in ToR switch ports facing the servers. A port that delivers 16 lanes of 25G can provide transceiver cost advantages compared to discrete transceivers. It also provides electrical signal routing advantages because all electrical lanes can be of nearly the same minimal length rather than spread out to reach ports across the entire switch faceplate which alleviates the need for repeater chips saving cost and power.

Regards,
Paul Kolesar

-----Original Message-----
From: Duwenhua [mailto:duwenhua@xxxxxxxxxxxxx]
Sent: Wednesday, June 24, 2015 3:36 AM
To: STDS-802-3-400G@xxxxxxxxxxxxxxxxx
Subject: [STDS-802-3-400G] one comment about 4x100G breakout RE: IEEE P802.3bs 400 Gb/s Ethernet Task Force Logic Ad Hoc

Hi, Martin

400GE FEC Breakout: (langhammer_02_0615_logic.pdf) pag5 said:
1x400G KP4 ASIC: 55645
1x400G KP4 & 4x100G KR4 ASIC: 61518
  11% area increase

My comments:
1) What is the size of 1x400G KP4 & 4x100G KP4 FEC?
2) today 100GbE choose KR4，but I think that the breakout 100GbE will need KP4 FEC if the 100GbE SMF PMD choose 100G PAM4 in future.
     --In long term, serial is better than parallel. For 100GbE, 100G PAM4 SMF PMD is better than 4x25G SMF PMD.
3) same idea can be seen at page29 of http://www.ieee802.org/3/bs/public/14_05/maki_3bs_01a_0514.pdf   QSFP28 has a DSP&FEC which convert 4x25G to 1x100G.

My conclusions:
1) 4x100G breakout, the FEC should be able to dynamic changed: 4x100G KR4, or 4x100G KP4.
2) 4x100G breakout is very important in data center switch at the positions of Spine switch and Core switch, because face port density and flexibility.
3) 8x50G and 16x25G breakout is not important, because only TOR switch need 50G/25GE, but TOR switch do not have 400GE port.

                         --Du Wenhua

-----Original Message-----
From: Mark Gustlin [mailto:mark.gustlin@xxxxxxxxxx]
Sent: Saturday, June 20, 2015 8:09 AM
To: STDS-802-3-400G@xxxxxxxxxxxxxxxxx
Subject: Re: [STDS-802-3-400G] IEEE P802.3bs 400 Gb/s Ethernet Task
Force Logic Ad Hoc

All,

Presentations are now up on the logic ad hoc web site from today's ad hoc call:
http://www.ieee802.org/3/bs/public/adhoc/logic/index.shtml

Thanks, Mark

-----Original Message-----
From: Mark Gustlin
Sent: Monday, June 15, 2015 10:59 AM
To: STDS-802-3-400G@xxxxxxxxxxxxxxxxx
Subject: RE: IEEE P802.3bs 400 Gb/s Ethernet Task Force Logic Ad Hoc

All,

Just a reminder of the upcoming logic ad hoc call.
The current agenda is:
400GE FEC Implementation - Martin Langhammer Considerations for
breakout - Martin Langhammer 1x400G vs 4x100G FEC Implications -
Bill Wilkie

Requests are due by end of day Wednesday. There is room for only one
more presentation for this call, so the next request will get the last slot.
There is another opportunity on June 29th.

Thanks, Mark Gustlin

From: Mark Gustlin [mailto:mark.gustlin@xxxxxxxxxx]
Sent: Thursday, June 04, 2015 2:49 PM
To: STDS-802-3-400G@xxxxxxxxxxxxxxxxx
Subject: [STDS-802-3-400G] IEEE P802.3bs 400 Gb/s Ethernet Task
Force Logic Ad Hoc

All,

This is an announcement of the next IEEE P802.3bs 400 Gb/s Ethernet
Task Force Logic Ad Hoc conference call opportunity.

The next call will take place on Friday June 19th from 8am-10am PDT.

If you are interested in presenting, please request a timeslot by
the end of Wednesday June 17th. A separate calendar invite will also follow.

In addition there will be another opportunity on Monday June 29th at
8am- 10am PDT.

Thanks, Mark Gustlin

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