Re: [802.3_4PPOE] [EXTERNAL] Re: [802.3_4PPOE] Classification Margin Sli

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Hi Lennart,

Thanks, please see below.

Yair

From: Lennart Yseboodt [mailto:lennart.yseboodt@xxxxxxxxxxx]
Sent: Thursday, May 17, 2018 11:28 AM
To: STDS-802-3-4PPOE@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_4PPOE] Classification Margin Slides- Review of David Abramson presentation by Yair

EXTERNAL EMAIL

Hi Yair,

First, nobody has suggested to allow Irev=1.3mA during classification, because this doesn't work. So we can discard that.

Yair: Yes I know, we are now in “0.5mA”. I was responding to earlier baseline number.

Let's take Class 0 and Class 1 as an example.

From the PSE's viewpoint it SHALL:

- current of 0 to 5mA == Class 0

- current of 5 to 8 mA == Class 0 or Class 1

- current of 8 to 13mA == Class 1

The PSE has 3mA of grey area in which it can put the Class 0 / Class 1 threshold.

Yair: Correct, and I want to concentrate on the case that the PSE threshold is set on one of the edges i.e. 5 or 8 mA.

The PD on the other hand has class current bands that are more narrow:

Class 0 is 1 to 4 mA

Class 1 is 9 to 12 mA

Yair: Correct.

By allowing Irev=0.5mA, we are essentially saying that now for the PD holds:

Class 0 is 1 to 4.5 mA

Class 1 is 9 to 12.5 mA

Yair: Yes I know and I said in my response to David A presentation that it is not the problem that I am addressing.

What changes for the PSE ? NOTHING. It still needs to

- current of 0 to 5mA == Class 0

- current of 5 to 8 mA == Class 0 or Class 1

- current of 8 to 13mA == Class 1

Yair: My main concern is:

there are PDs in the market that deviates from the PD requirements by up to 1mA e.g. 0.5mA since they utilize the (5-4)=1mA gape.

So PDs that was used to be OK with legacy PSEs will not be with Type 3 and 4 PSEs due to the guaranteed addional “0.5mA”. This issue worry me it is kind of interoperability issue although you can argue it by saying that the PD is not compliant.. there are millions of such PDs that where OK with Type 1 and 2 PSEs allowed margins. Now the margin will be short by 0.5mA.

There is no impact on PSE classification current margin.

Kind regards,

Lennart

On Thu, 2018-05-17 at 08:09 +0000, Yair Darshan wrote:

Hi David,

Many thanks for this work.

It allows me to show, that we are missing the point that some of us are trying to make. Please see details in the file attached.

Short summary of my inputs:

The issue is not the 1mA margin between the PSE and PD requirements.

The problem is; In the example, you took (and problem is the same for any class we will take) the PSE put its threshold for deciding Class 0 or Class 1 at 6.5mA.

If PD will use the normal Iclass, the margin between this PSE threshold to the maximum class 0 current will be (6.5-4)=2.5mA. This is +/-38.46% margin.

Now if we allow 0.5mA more to Iclass, the margin will be reduced to 30.77%. This means that legacy PDs that worked well with legacy PSEs, now may fail to show the correct Iclass with Type 3 and 4 PSEs operating in 3-pair mode. This is interoperability issue.

The problem gets worse if we allow 1.3mA. In this case the margin drops to 18.46% only.

See more for some of the assumptions you have used which are incorrect and some are correct but doesn’t change the above problem.

So, obviously the 0.5mA reduces the magnitude of the problem but still it is major interoperability problem also with 0.5mA too.

I’ll appreciate your response.

Yair

From: Abramson, David [mailto:000009c91bbcc8ad-dmarc-request@xxxxxxxx]
Sent: Monday, May 14, 2018 11:50 PM
To: STDS-802-3-4PPOE@xxxxxxxxxxxxxxxxx
Subject: [802.3_4PPOE] Classification Margin Slides

EXTERNAL EMAIL

Hi everyone,

I put together a few slides with some thoughts about classification margin and some other ideas. They are attached.

Regards,

David Abramson

IC Design

Power Interface

Texas Instruments

Office: 603.222.8519

Mobile: 603.410.7884

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Re: [802.3_4PPOE] [EXTERNAL] Re: [802.3_4PPOE] Classification Margin Slides- Review of David Abramson presentation by Yair