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Hi Mike,
This is broadly similar to, but not exactly what we do for ER. 30km is guaranteed to be plug and play with max. fiber loss. 40km is not supported with max. fiber loss.
We can do likewise by reducing the connector and splice loss allocation. For example, the DR the channel insertion loss could be 2dB instead of 3dB.
Chris
From: Mike Dudek <mdudek@xxxxxxxxxxx>
Sent: Wednesday, August 16, 2023 12:27 PM
To: STDS-802-3-B400G@xxxxxxxxxxxxxxxxx <STDS-802-3-B400G@xxxxxxxxxxxxxxxxx>
Subject: Re: [802.3_B400G] [802.3_B400G_LOGIC] P802.3dj Joint Logic/Optics Track ad hoc agenda 8/15/23
To me what makes it one phy versus two phys is the following.
All compliant devices must be inter-operable and meet the defined objective in their default mode. Having additional (optional or required) defined modes (e.g. FEC in 10GBASE-KR) or bypass inner FEC MODE for 200GBASE-DR does not make it two phys provided
there is the mandatory inter-operable mode that is the default and meets the objective. (Whether operation at other than the default is changed via auto-negotiation or an engineered solution doesn’t in my opinion change whether it is one phy.).
Sticking with the idea of the two modes but one Phy we could decide that in bypass mode the guaranteed link budget and reach is less (i.e. channel is better as Chris and Tom have suggested) and then , if my suggestion of auto-negotiation based on achieved error
rate is used, the statistics of Tx’s and Rx’s being better than worst case will actually mean the majority of links can operate in the Bypass mode at the defined objective. (This would only guarantee the lower power and latency with the better channel but
could be significant statistical help for data center power dissipation and latency). A 2dB link budget reduction would I think compensate for much of the difference in required BER with the FEC bypassed. It could be achieved by relaxing the TDEC max
and TDECQ max for the KP4 only Probability by 2dB and reducing the min OMA-TDECQ/TDEC by 2dB. A reduction in length to 100m might also be worthwhile and at that length I don’t see a need to have a TDECQ spec TDEC should be fine by itself. Note that
if people are worried about latency they shouldn’t be having >100m lengths of fiber as this is approx 500ns latency which is way more latency than the inner FEC).
From: Chris Cole <chris.cole@xxxxxxxxxxxx>
Sent: Wednesday, August 16, 2023 10:14 AM
To: STDS-802-3-B400G@xxxxxxxxxxxxxxxxx
Subject: [EXT] Re: [802.3_B400G] [802.3_B400G_LOGIC] P802.3dj Joint Logic/Optics Track ad hoc agenda 8/15/23
External Email
If I drive the same car at two different speeds, that doesn't make it two cars.
All
I will be discussing this topic further with Mr. Law shortly.
Despite assertions it is the same device - the current tx proposal is not the same device running at lower rates as there were other changes to the tx / tx proposed.
Your patience is appreciated
If inner FEC is specified for plug and play DR and FR, the specifications for the no inner FEC mode falls out of it. It's the same implementation operating at the lower rate. This leads to reduced performance, for
example lower power budget. Whether that's useful is a separate question.
Given the confidence by TF participants in no inner FEC feasibility, we should revisit writing a spec. for only this case. This is especially true for DR.
One option is to specify DR only with end-to-end FEC, and FR and LR are with inner FEC, again subject to demonstrating feasibility.
Subject Re: [802.3_B400G] [802.3_B400G_LOGIC] P802.3dj Joint Logic/Optics Track ad hoc agenda 8/15/23
Hello Chris,
One of the key reason for success of IEEE 802.3 standards as said is the Five Criteria (CSD) and technical feasibility, on the DJ website under Technical Feasibility we have:
At a minimum, address the following items to demonstrate technical feasibility:
a) Demonstrated system feasibility.
b) Proven similar technology via testing, modeling, simulation, etc.
c) Confidence in reliability.
I am sure at some point in time 200 Gb/s/lane optics will evolve sufficiently where one with confidence and reliable operate such link with just KP4 FEC.
If for some reason the future TX technology (2nd Gen Sipho/TFLN ??) are ready for deployment in 12-18 months then there is no reason to define PMDs with inner FEC!
We should not hack defining future optics PMDs based on 1st Gen 200G TX optics!
Thanks,
Ali Ghiasi
Ghiasi Quantum LLC
One perspective is that we create new objectives for the same reach, with independent specs. at a lower rate and only end to end FEC. Part of the motivation is that a better TX modulator removes the need for inner FEC. If we adopt this approach, we will have
two solutions to the same problem: 1) "bad" TX with inner FEC to make up for the badness, 2) "great" TX without the need for inner FEC. Unfortunately, we have 802.3 Five Criteria to contend with. Distinct Identity clearly states there will be one solution
to one problem. If DI doesn't apply here, then we might as well discard it, and going forward only have 802.3 Four Criteria.
FEC bypass should be a lower performance operating mode for the same HW. This is the basis on which I supported moving forward with it. We have to add a full set of specifications for this mode. This is why the general approach we take for ER is good precedent.
The Plug-and-play spec column is at the higher rate with inner FEC. The Engineered spec column is at the lower rate with inner FEC bypassed. An end user can then look at the spec, and for example conclude that for their shorter reach ML clusters, the FEC bypassed
mode works just fine. However, the specifications lead to one component type. The industry does not need component type proliferation driven by IEEE. That leads to market fragmentation.
Alternatively, if we really believe that "good" TX technology is available, let's not bother having an inner FEC. Let's forget writing a spec for "bad' TX and write one spec. for end-to-end FEC only.
Either way, we do not need new objectives. We have single 500m and 2km objectives, each with two modes (Plug-and-play and Engineered) with different levels of performance and operating parameters like rate, or just one Plug-and-play mode without inner FEC.
Hi Everyone,
All files for tomorrow’s joint optics/logic ad hoc meeting are posted
here
[ieee802.org].
Call in details are available here
[ieee802.org].
The technical presentations in the agenda are:
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" FEC Bypass: Procedural Considerations " presented by John D’Ambrosia, Futurewei, US Subsidiary of Huawei
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" Performance Evaluation of Inner FEC Synchronization Methods " presented by Xiang He, Huawei
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" Specifying BER in PMD clauses " presented by Adee Ran, Cisco
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" DGDmax specification for 10km Ethernet" presented by Maxim Kuschnerov, Huawei
We may be holding a straw poll after the first presentation to gather directional feedback for Task Force leadership.
I want to remind all teleconference meeting participants to review the following documents prior to participation in an IEEE 802.3 meeting teleconference:
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IEEE SA patent policy
-
IEEE SA Copyright Policy
-
IEEE SA Participation Policy
IEEE P802.3dj optics track leader
IEEE P802.3dj architecture and logic track leader
Reminder to everyone about next Tuesday’s IEEE P802.3dj joint logic and optics track ad hoc meetings.
There are deadlines this week for agenda requests (Wednesday) and presentation submission (Friday).
Regards,
Mark
This email serves to announce the next IEEE P802.3dj joint logic and optics track ad hoc meetings.
Meeting dates, times and deadlines:
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Agenda request deadline (5pm PT)
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Contribution submission deadline (5pm PT)
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Tues Aug 15th, 7am to 10am PT
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Tues Aug 29th, 7am to 10am PT
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Coming out of the May plenary meeting, we identified a number of areas where more information is needed or more consensus is needed. The purpose of these ad hoc meetings is allow discussion and contributions on any of these topics. We are holding it joint
between the optics and logic teams as a number of these topics relate across both areas.
The goal will be to enable contributors to better refine proposals or provide information relevant to future decisions ahead of the July Plenary meeting. With this being an ad hoc meeting, no decisions can be made but informative straw polls are possible.
At this point, we anticipate topics to potentially include:
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Inner FEC padding and synchronization
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FEC bypass proposal
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Updates on IMDD optical baseline proposals (nothing adopted yet)
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Updates on coherent optical baseline proposals (nothing adopted yet here too)
But this is not a complete list of potential topics.
If anyone, does wish to make a short presentation in line with above please make a request by the dates noted above. Please email myself, Mark Gustlin (and John D'Ambrosia, please) the following information:
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Name of presenter
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Affiliation of presenter
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Title of presentation
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Length of time requested (this should include time for questions and answers – presentation time, excluding Q&A, will be at the discretion of the chair, and should be assumed to be limited to 30 min)
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Brief description of topic
The presenter shall e-mail a PDF, soft-copy version of the presentation to me (and John D'Ambrosia, please) in advance of the meeting per above dates..
Please adhere to the Presentation Style Guidelines. Also, to support the web site search tool used by the IEEE P802.3 web site the 'Document Information' fields of the PDF file must be completed as follows:
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Title: Title of presentation
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Author: Name(s) of author(s)
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Subject: IEEE P802.3dj Task Force
I want to remind all teleconference meeting participants to review the following documents prior to participation in an IEEE 802.3 meeting teleconference:
-
IEEE SA patent policy
-
IEEE SA Copyright Policy
-
IEEE SA Participation Policy
IEEE P802.3dj optics track leader
IEEE P802.3dj architecture and logic track leader
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