Hi Wei,
Thank you once again for your prompt reply.
Below is a “simplified” action diagram for the TRAINING0 state that I constructed based your description:
“When tx_mode=SEND_TS, this is the symmetric training mode, the pcs_tx_mode will alternate between T_2p5G and QUIET,
to generate symmetric training TDD ON/OFF cycles. When it is T_2p5G, PCS will transmit 3Gsps PAM2 training frames. When it is QUIET, PCS will send zero.”
The action diagram shows that the Master and Slave are ping-ponging transmit signals, and when quiet the receiver will train on the signal received from the other side.
There were several things that I “simplified” in the action diagram below, including the synchronization of the Master and Slave transmit slots, and how to handle the Intra-Burst Gap (IBG). I also assumed
(based on Figure 2-32 of baseline text for the New-TDD) that the slave already had done most of its training in the SILET0 state and already had the detect_lp_burst variable set to TRUE.
Regarding the clock synchronization (CDR), 1ppm clock offset between Master and Slave would result in 9.6ps drift per each 9600ns TDD cycle. This means that if the clock offset in 100ppm (e.g., Master 50ppm
to slow and Slave 50ppm to fast), then the clock drift is 960ps. For comparison, the symbol interval at 2.5Gbps is 400ps, so this is more than two whole symbols. It is imperative to deal with this potential clock drift, but it was not clear to me from the
text how to deal with the such drift in an interoperable way. In particular, I see that there is no timing_lock_OK bit in the Infofield in Table 200-10.
I now have the following questions for you:
- Is the enclosed “simplified” action diagram correct?
- How do the master and slave synchronize their start of transmissions during the Training0 state?
- Do I understand correctly that the Slave has already mostly completed its training before it enters the TRAINING0 state?
- How is CDR synchronization done? Will the Slave already have locked on to the Masters clock before it enters the TRAINING0 state?
- If there is a clock drift between the Master and Slave during TRAINING0, is it always the Slaves responsibility to correct it, or should the Master also
change its clock phase during this time?
- Why is the timing_lock_OK bit no longer needed? How will the Master know that the Slave is no longer making significant adjustments to its clock?
Ragnar
From: Wei Lou <000047a3c8c56bbe-dmarc-request@xxxxxxxxxxxxxxxxx>
Sent: Tuesday, July 8, 2025 11:55 AM
To: STDS-802-3-ISAAC@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_ISAAC] [EXTERNAL] Re: [802.3_ISAAC] Question on Baseline Text Proposal for TDD Based 802.3dm PHY
Hi, Ragnar, Thank you for raising this question. The tx_mode is from the PMA/PHYC and it tells the PCS what is the current transmit mode ( SEND_TS, SEND_TA, SEND_TA_EXT,
SEND_N and SEND_Z). The non SEND_Z mode representing the corresponding
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Hi, Ragnar,
Thank you for raising this question. The tx_mode is from the PMA/PHYC and it tells the PCS what is the current transmit mode ( SEND_TS, SEND_TA, SEND_TA_EXT, SEND_N and SEND_Z). The non SEND_Z mode representing the corresponding repeating TDD ON/OFF cycles in symmetric training, asymmetric training, extended asymmetric training and data mode. It does not contain the specific transmit modulation/speed information, as well as TDD ON/OFF duration, etc. It reflects a general PHYC state.
pcs_tx_mode(TBD) is a pcs internal variable, which tells PCS what signals to send out to PMA at each symbol time (tx_symb). It controls modulation, speed, TX ON/OFF cycles durations.
When tx_mode=SEND_TS, this is the symmetric training mode, the pcs_tx_mode will alternate between T_2p5G and QUIET, to generate symmetric training TDD ON/OFF cycles. When it is T_2p5G, PCS will transmit 3Gsps PAM2 training frames. When it is QUIET, PCS will send zero.
When tx_mode=SEND_TA, this is asymmetric training mode, the pcs_tx_mode will alternate between T_PAM2 and QUIET, to generate PAM 2 asymmetric training TDD ON/OFF cycles. When it is T_PAM2, the 100M+MultiGBASE-T1/V1 will send 3Gsps PAM2 training frames. The 2.5G+100MBASE-T1/V1 will send 3Gsps PAM2 training frames. While the 5G/10G+100MBASE-T1/V1 will send 6Gsps PAM2 training frames.
When tx_mode=SEND_TA_EXT, this is the asymmetric extended training mode only used for 10G+100MBASE-T1/V1 and 100M+10GBASE-T1/V1, the pcs_tx_mode will alternate between T_PAM2_4 and QUIET. For 100M+10GBASE-T1/V1, T_PAM2_4 will send 3Gsps PAM2 training frames. For 10G+100MBASE-T1/V1, T_PAM2_4 will send 6Gsps PAM2(during Refresh header) and PAM4 (during training payload).
Hope this clarifies your question. Thanks.
Wei
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