Re: [802.3_ISAAC] [EXTERNAL] Re: [802.3_ISAAC] Question on Baseline Text Proposal for TDD Based 802.3dm PHY
Hi, Ragnar,
Generally, to address the questions you raised, please refer to TDD proposal's PHY control state diagram which specifies that loc_rcvr_status0= OK is the condition for SLAVE to change from SILENT0 to TRAINING0. loc_rcvr_status=OK means " The PMA Receive function uses the parameters pcs_status and scr_status, and the state of the
equalization, and estimation functions to determine the quality of the receiver performance, and generates the loc_rcvr_status variable accordingly." (Section 200.6.2.3)
Based on this definition, the timing_lock= OK is implied when loc_rcvr_status=OK. Other criteria include sufficient SNR margin, etc.
The MASTER will not adjust its transmit clock frequency during the entire training/data mode. It sends out fixed periodic TDD pattern during each Training phase. It will adjust its TDD QUIET/burst duration from Symmetric training to Asymmetric training. SLAVE is responsible to synchronize to MASTER clock.
Wei
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