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Re: [802.3_ISAAC] [EXTERNAL] Re: [802.3_ISAAC] Question on Baseline Text Proposal for TDD Based 802.3dm PHY

Hi Wei,

 

Thank you once again for your prompt response.

 

As you can probably tell, I am reading through the New-TDD baseline text in detail, but I was still not sure about the timing relationship between Master and Slave. Thank you for clarifying this relationship.

 

Regarding the definition of the loc_rcvr_status, I found several statements about loc_rcvr_status:

  1. According to Clause 200.2.2.7 of New-TDD baseline text, “The criteria for setting the parameter loc_rcvr_(n)_status is left to the implementer.” I assume that loc_rcvr_(n)_status is same as loc_rcvr_status0, for n=0.
  2. According to Clause 200.4.2.3 of the New-TDD baseline text, “When loc_rcvr_status indicates OK, then the PCS Synchronization process accepts data-units via the PMA_UNITDATA.indication primitive.” I understood this to mean that the PCS Synchronization process will only start after loc_rcvr_status is OK.
  3. According to Clause 200.6.2.3 of the New-TDD baseline text, “The PMA Receive function uses the parameters pcs_status and scr_status, and the state of the equalization, and estimation functions to determine the quality of the receiver performance, and generates the loc_rcvr_status variable accordingly.” I understand this to mean that that frame synchronization may be required before loc_rcvr_status becomes OK.
  4. According to Clause 200.6.4.1 of the New-TDD baseline text,  the loc_rcvr_status variable indicates “correct or incorrect operation of the receive link for the local PHY at the current TRAINING stage.” This suggests to me that there may be more than one valid criterion for setting loc_rcvr_status to OK.

The c-variant above is the same as in 802.3ch, but b-variant may be conflicting with the c-variant. This is why I was not sure how to interpretate loc_rcvr_state set to OK. You have now clarified this for me.

 

I have created the action diagram below for the SILENT0 state (the second state) in the state diagram in Figure 200-32 in the New-TDD baseline text. Do you think that I am representing correctly what is expected to happen in the Master and Slave PHYs in the SILENT0 phase?

 

Ragnar

 

 

From: Wei Lou <000047a3c8c56bbe-dmarc-request@xxxxxxxxxxxxxxxxx>
Sent: Thursday, July 10, 2025 9:08 AM
To: STDS-802-3-ISAAC@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_ISAAC] [EXTERNAL] Re: [802.3_ISAAC] Question on Baseline Text Proposal for TDD Based 802.3dm PHY

 

Hi, Ragnar, Generally, to address the questions you raised, please refer to TDD proposal's PHY control state diagram which specifies that loc_rcvr_status0= OK is the condition for SLAVE to change from SILENT0 to TRAINING0. loc_rcvr_status=OK

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Hi, Ragnar,
Generally, to address the questions you raised, please refer to TDD proposal's PHY control state diagram which specifies that loc_rcvr_status0= OK is the condition for SLAVE to change from SILENT0 to TRAINING0. loc_rcvr_status=OK means " The PMA Receive function uses the parameters pcs_status and scr_status, and the state of the
equalization, and estimation functions to determine the quality of the receiver performance, and generates the loc_rcvr_status variable accordingly." (Section 200.6.2.3)
Based on this definition, the timing_lock= OK is implied when loc_rcvr_status=OK. Other criteria include sufficient SNR margin, etc.
The MASTER will not adjust its transmit clock frequency during the entire training/data mode. It sends out fixed periodic TDD pattern during each Training phase. It will adjust its TDD QUIET/burst  duration from Symmetric training to Asymmetric training. SLAVE is responsible to synchronize to MASTER clock.
 
Wei
 
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