Hi TingTing,
If we interleave, that will really increase the latency if FEC is turned on for the long reach case.
Roughly back of the envelope the lengths of the RS-frame is about 7000ns. And let’s say
the remaining algorithm latency is about 1000ns. So we start with a PHY with 8000ns algorithm latency.
If we interleave 2x then we need twice the time to accumulate the data for the syndrome calculation
hence 8000ns + 7000ns = 15000ns. This is not a good tradeoff in my opinion.
The 100BASE-T1 3B2T code is not intrinsically safe and it was not designed to be.
The only thing reducing the probability of DC accumulation is it has a decent scrambler.
If we get a run of nothing but say 000, 001, 011 or alternatively 111, 110, 100 the unbalance is going to accumulate.
Thanks,
William
From: zhangtingting (O) <00001e92abc91102-dmarc-request@xxxxxxxxxxxxxxxxx>
Sent: Friday, January 12, 2024 03:31
To: STDS-802-3-SPEP2P@xxxxxxxxxxxxxxxxx
Subject: [802.3_SPEP2P] 答复: Question on 8b10b to PAM4
Hi William,
FEC for 802.3dg is used to correct the errors induced by the EFT and the residual ringing. Two separate 8B/10B encoders might require slightly
higher error correction capability (George also pointed out during November’s meeting). A straight way to deal with this is using interleaving (depth of 2 is enough).
100BASE-T1 for automotive has already constrained PHY delay to be less than 1.32us (in Clause 96.10), which is lower than 1.5us for motor feedback
application. The only question is how large the difference between the two link segments is. If the motor feedback cabling (AWG22) is good enough, 100BASE-T1 PHY might cover this application.
Finally, if 802.3dg PHY baseline can have the same symbol rate as 100BASE-T1 (66.66MBaud), PMA can be shared at the most between 100BASE-T1L and
100BASE-T1. A dual-mode 100M SPE PHY for many applications is possible then, which I think will be good for SPE ecosystem.
Best wishes,
Tingting
发件人:
William Lo [mailto:will@xxxxxxxxxx]
发送时间: 2024年1月12日 16:13
收件人: zhangtingting (O) <zhangtingting59@xxxxxxxxxx>;
STDS-802-3-SPEP2P@xxxxxxxxxxxxxxxxx
主题: RE: Question on 8b10b to PAM4
Hi Tingting,
Thanks for clarifying.
This is a very clever way to not just to suppress DC but guarantee a bound on the PAM4 disparity.
There is one issue I see with this and that is if one PAM4 symbol
gets damaged, both 8/10 symbols can potentially be corrupted
meaning two RS-symbols are corrupted instead of just 1.
This severely weakens the FEC protection given that there are
only 6 parity symbols in most of the proposals (I agree that 6 RS symbols is
a good number). If 2 PAM4 symbols are corrupted in the same
RS frame and it propagates to 4 RS symbol errors then the frame
is uncorrectable.
If there is a way to contain the PAM4 symbol corruption to only one RS symbol error
then it would be good.
Thanks,
William
From: zhangtingting (O) <zhangtingting59@xxxxxxxxxx>
Sent: Thursday, January 11, 2024 19:10
To: William Lo <will@xxxxxxxxxx>;
STDS-802-3-SPEP2P@xxxxxxxxxxxxxxxxx
Subject: 答复: Question on 8b10b to PAM4
Hi William,
Each PAM4 symbol has two bits (LSB and MSB), which are separately encoded by 8B/10B before the
binary symbol mapper instead of the commonly used Gray mapper. In this way, DC components should be well suppressed. Let me know if you have any further questions.
Best wishes,
Tingting
发件人:
William Lo [mailto:will@xxxxxxxxxx]
发送时间: 2024年1月12日 2:17
收件人:
STDS-802-3-SPEP2P@xxxxxxxxxxxxxxxxx
主题: [802.3_SPEP2P] Question on 8b10b to PAM4
Hi Tingting,
You mentioned in the ad hoc that my assumptions on doing the
8b/10b to PAM4 conversion was incorrect. I tried using that method
and the PSD near DC didn’t look very good. Can you show me the
right way to do the conversion.
Thanks,
William
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