[Mellitz, Richard] my comments below
From:
owner-stds-802-3-blade@LISTSERV.IEEE.ORG
[mailto:owner-stds-802-3-blade@LISTSERV.IEEE.ORG] On Behalf Of Joe M Abler
Sent: Monday, November 29, 2004
6:50 PM
To:
STDS-802-3-BLADE@LISTSERV.IEEE.ORG
Subject: [BP] Parameter input to
signaling spreadsheet
.
Here's
my input on the signaling comparison spreadsheet, specifically for the
"Source Data Parameters" section.
On
existing entries:
- My suggestion for Data
Pattern is to use a random stream. [Mellitz, Richard] Do you have any suggestion
on the random stream?
- Launch amplitude should be
the minimum value proposed to the standard for the particular signaling
method.
- Tx jitter should be split
into both DJ and RJ, and should be set to the worst case value proposed to
the standard for the particular signaling method.
- Tx jitter should also
include worst case DCD. This would go hand in hand with a statement
that all simulators account for what's been termed phase noise
amplification. If that's not accounted for by all, then it should be
excluded by all such that we have equivalent comparison. [Mellitz, Richard] Would all the DCD go into DJ?...
or do you have a good way of allocating. FYI, we call the effect
that DCD has, channel jitter amplification and be as high 3 timesTx DCD DJ
at Rx. I think it plays into a signaling decision.
- Rx allocated jitter should
also identify both DJ and RJ. I would suggest that the worst case
values proposed by an implementation be used. This would likely lead
to different values being used in different simulations, and these
differences would need to be accounted for in the complexity section (i.e.
a design with a significantly lower RJ would be a higher power design). If
this second order comparison is expected to be too difficult, then we
should plan to use common values. Note that the current spreadsheet
lists entries for Rx Input DJ & RJ. I find the term
"Input" a bit confusing since it could imply that it is the
jitter seen at the input to the receiver (which is of course determined by
the Tx jitter and the channel), but I assume this is meant to be the same
as what I'm calling Rx allocated jitter, which is the amount of jitter
associated with the receiver design, clock generation, etc.
- AC/DC coupling. I
would say we need someone to contribute a set of s-parameters for the AC
coupling section of an actual design. If that's not available in the
short term, then I would suggest we not hold up simulations waiting for
it. I don't believe that excluding it would affect the signaling
decision. We still will need to have this eventually since it's
effect needs to be accounted for in setting the normative channel model.[Mellitz, Richard] I agree, this is very
important to a design. It basically adds a little more ripple and via notches
above 7GHz to the pass band. Routing of caps on a board can be a major source
of crosstalk on some designs. I think we ignored it in tp1-4 because there
are lot of design options that may or may not be driven by the rx chips. At
one time I suggested that if deviates significantly from a “clean cap
route” it goes it the tp1-4 budget from a board designers perspective.
Entries which I suggest be added:
- Termination tolerance
skew. Should be set to worst case skew proposed to the standard for
the particular signaling method.
[Mellitz, Richard]
How about capacitance and resistance linearity?
- Tx & Rx IC models. Either
need to agree to a common model or some measure of accounting for
complexity. Should not be using an ideal model.
- Tx launch signal. This
goes somewhat hand-in-hand with the Tx IC model. If we have a
realistic model, then it would be reasonable to use a square wave input. If
we end up with an ideal IC model (which I wouldn't recommend), then we
should at least be using a slew-rate limited launch signal. [Mellitz,
Richard] Good
point. Are we actually simulating the Tx or doing FD/TD math magic?
- Receiver frequency
offset. Should be set to worst case proposed to the standard for a
particular signaling method.
- Receiver minimum latch
overdrive value. I suggest 15mV.
- Common package model is
needed.
[Mellitz, Richard]
Package RL of x db can be capacitive and inductive. (Both sides of the Smith Chart)
Need to consider both. Can we agree on a package model circuit?
- Simulation time, in terms
of number of bits, should be common. I suggest 10M bit times to
properly account for xtalk.
And then final input is on the channels themselves. I believe we
should exclude any channels from the simulation set that don't include
xtalk because with it they are simply too incomplete to be included in
the decision making process.
Thanks, Joe
Joe Abler
abler@us.ibm.com
IBM Microelectronics Division
919-254-0573
Technical Marketing & HSS Applications 919-254-9616
(fax)
3039 Cornwallis Road
Research Triangle Park, NC
27709
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