Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

Re: [BP] Channels for simulation - Attn: Bill Peters

Joe, et al,
We at Xilinx have been simulating the following Intel channels.  We made the selection based on them being representative permutations of length and stub depth.  Basically the variables are Bottom / Middle / Top vs. 1"(7.2") / 20"(25.9") / 32"(37.9").
BrianS

peters_01_0904_B1_thru.s4p
peters_01_0904_B20_thru.s4p
peters_01_0904_B32_thru.s4p
peters_01_0904_M1_thru.s4p
peters_01_0904_M20_thru.s4p
peters_01_0904_M32_thru.s4p
peters_01_0904_T1_thru.s4p
peters_01_0904_T20_thru.s4p
peters_01_0904_T32_thru.s4p
 

Joe M Abler wrote:

 
At the January meeting we identified a few steps to make our simulation workload more manageable.  We made progress on this at the last signaling ad-hoc by zeroing in on an single package model and limiting the IC model and TP4-TP5 requirements.  The other request we made is to pick a subset of the Intel channels to simulate against since there was a large number of these.  Bill, you had agreed you would be able to pick the subset you'd like us to focus on.  Have you been able to look at that?  I don't see anything out on the website nor have I seen any reflector traffic.  We also targeted to have simulation results input by Feb 28, which is coming up real fast.  I'd appreciate if you could provide us input.
 

Thanks,        Joe
 

Joe Abler                                                             abler@us.ibm.com
IBM Microelectronics Division                          919-254-0573
Technical Marketing & HSS Applications    919-254-9616 (fax)
3039 Cornwallis Road
Research Triangle Park, NC  27709

begin:vcard
n:Seemann;Brian
tel;work:952-769-0067
x-mozilla-html:TRUE
url:www.xilinx.com
org:Xilinx;Communication Technology Division
version:2.1
email;internet:Brian.Seemann@xilinx.com
title:Director, Business Management
adr;quoted-printable:;;7901 Xerxes Avenue South=0D=0ASuite 316;Minneapolis;MN;55431;USA
fn:Brian Seemann
end:vcard