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Magesh, Rich and I had presented similar findings some time ago, when we had looked at settling time and the impact of varying the location of the DC blocking cap on the Rx line card. I don’t recall the presentation # offhand, and will try to find it.
John
-----Original Message-----
I wanted to bring up an issue related to the consistency of simulated performance of a channel and its comparison to the channel limit lines. In our simulations, we observed that the magnitude of reflections in the cascaded pulse responses was not consistent with the backplane return loss and ILD frequency responses. Further study showed that the exact delays between the TX driver, connectors and load have a significant impact. The reflections are mostly high frequency artifacts and are very phase sensitive, especially at 10G, where 5mm of trace length can cause more than 0.5UI shift in the reflections in the pulse response. Considering variations in package models and routing this should be considered.
By cascading two 50 ohm transmission lines at the ends of backplane models, and varying the length of each from 0 to 15mm, I can vary the BER performance of the channel by several orders of magnitude.
Attached is a slide that shows the pulse responses for Tyco Case 5 and Case 7 backplanes with a slightly modified Mellitz Cap like package model on both sides. (Pad+ESD cap reduced to 0.63pF to allow 45 ohm to 55ohm DC impedance drivers to pass the D2.3 RL spec).
Tyco case 5: 2mm on the RX side, BER = 8e-21 Tyco case 5: 11mm on the RX side, BER = 4e-15
Tyco case 7: 3mm on the TX side, BER = 5e-19 Tyco case 7: 6.5mm on the RX side, BER = 1e-12
This is one instance where a phase insensitive magnitude based ILD and Return Loss channel specification can flag a problem, but a single instance of a simulation can not. More sims are being run under this worst case condition to investigate channel limit lines.
Magesh |