Re: [BP] Reflection alignment and BER
All,
In comparing our simulations with the current limit lines in Annex 69B
there are several false positives and false negatives. I intend to
propose some changes to these limit lines such that there are no false
positves and the few false negatives have been relegated to just two of
the recent Avago channels, that Charles has so kindly developed for us
to analyze ripple in the s21. We will have a presentation in Denver that
illustrates these changes and our simulations. I wanted to get this out
as soon as I could so everyone can take a look at them ahead of time,
start some dialog or at least be better prepared for discussion in
Denver. The proposed limit changes are:
A (Fitted Attenuation)
------------------------
Calculated from 100MHz to 9GHz
Limit: 100MHz<=f<=380MHz A<=Amax=3.18+3.21e-9*f
380MHZ<f<=15GHz A<=Amax=2.74+4.36e-9*f
IL (Insertion Loss)
--------------------
Limit: 100MHz<=f<=6GHz IL<=Amax+0.8+2.65e-10*f
6GHz<f<=15GHz IL=Amax+0.8+2.65e-10*f + 3.5e-9*(f-6GHz)
ILD (Insertion Loss Deviation)
-------------------------------
Calculation same as D2.3
Limit: 100MHz<=f<=10.3125GHz, -2.77-4.36e-10*f <= ILD <= 2.77+4.36e10*f
RL (Return Loss)
------------------
Limit: 50MHz<=f<3GHz, RL>22+9.56*log10(f/50MHz)
3GHz<=f<=10.3125GHz, RL>5
ICRfit (Fitted Insertion loss to Crosstalk Ratio)
------------------------------------------------
Calculation same as D2.3
Limit: 100MHZ<=f<350MHz, ICRfir>= 47-15.62*log10(f/100MHz)
350MHz<f<10.3125GHz, ICRfit>=39-20.21*log10(f/350MHz)
I have also included a summary of our simulation results and the
comparison to D2.3 limit lines and our proposed limit lines.
Howard
DAmbrosia, John F wrote:
> Magesh,
>
> Rich and I had presented similar findings some time ago, when we had
> looked at settling time and the impact of varying the location of the
> DC blocking cap on the Rx line card. I don’t recall the presentation #
> offhand, and will try to find it.
>
> John
>
> -----Original Message-----
> *From:* Magesh Valliappan [mailto:mageshv@BROADCOM.COM]
> *Sent:* Wednesday, March 01, 2006 2:54 PM
> *To:* STDS-802-3-BLADE@listserv.ieee.org
> *Subject:* [BP] Reflection alignment and BER
>
> I wanted to bring up an issue related to the consistency of simulated
> performance of a channel and its comparison to the channel limit lines.
>
> In our simulations, we observed that the magnitude of reflections in
> the cascaded pulse responses was not consistent with the backplane
> return loss and ILD frequency responses. Further study showed that the
> exact delays between the TX driver, connectors and load have a
> significant impact. The reflections are mostly high frequency
> artifacts and are very phase sensitive, especially at 10G, where 5mm
> of trace length can cause more than 0.5UI shift in the reflections in
> the pulse response. Considering variations in package models and
> routing this should be considered.
>
> By cascading two 50 ohm transmission lines at the ends of backplane
> models, and varying the length of each from 0 to 15mm, I can vary the
> BER performance of the channel by several orders of magnitude.
>
> Attached is a slide that shows the pulse responses for Tyco Case 5 and
> Case 7 backplanes with a slightly modified Mellitz Cap like package
> model on both sides. (Pad+ESD cap reduced to 0.63pF to allow 45 ohm to
> 55ohm DC impedance drivers to pass the D2.3 RL spec).
>
> Tyco case 5: 2mm on the RX side, BER = 8e-21
>
> Tyco case 5: 11mm on the RX side, BER = 4e-15
>
> Tyco case 7: 3mm on the TX side, BER = 5e-19
>
> Tyco case 7: 6.5mm on the RX side, BER = 1e-12
>
> This is one instance where a phase insensitive magnitude based ILD and
> Return Loss channel specification can flag a problem, but a single
> instance of a simulation can not. More sims are being run under this
> worst case condition to investigate channel limit lines.
>
> Magesh
>
KR_limits_summary.pdf