[RE] Outline for presentation on various choices for synch transport in ResE

["Geoffrey M. Garner" <gmgarner@xxxxxxxxxxx>]

In the ResE technical conference call yesterday I agreed that I would 
prepare a presentation for
the upcoming meeting summarizing the various choices/possibilities for synch 
transport in ResE.  It was asked if
I would send an outline to the reflector in advance.  The title and outline 
are:

Title:  Summary of Potential Choices for Synchronization Transport in 
Residential Ethernet

Outline
- Introduction
§- Basic time stamp scheme
§- Variations/choices
.         - Instantaneous phase adjustments at intermediate nodes
.         -Instantaneous phase and frequency adjustments at intermediate 
nodes (with instantaneous frequency adjustments possibly less frequent)
.         -Filtered phase adjustments at intermediate nodes, using digital 
filter running at local clock rate
.         -Full phase-locked loops (PLLs) at intermediate nodes (i.e., 
filtered phase and frequency adjustments)
.         -Use of transparent clock nodes
.         -Time stamp reflects current time versus delay by some number of 
frames
.         -Time stamp reflects local free-running clock time versus latest 
corrected time based on most recent time stamps and possible filtering)

I expect the presentation to be around 10-12 slides; as discussed in the 
call, this will be a summary and will not contain a huge amount of detail 
(the detail will likely be given later when the various choices are 
analyzed).

Any comments would be welcome.

Thanks.

Best regards,

Geoff
---------------------------------------------------------
Geoffrey M. Garner
Samsung (Consultant)