Re: [8023-10GEPON] Example of why doing FEC after scrambling need s careful analysis
Franks,
Thanks, and it was nice to meet you this week.
I do agree that it is likely to be possible to design a FEC that has the right properties. In my first email I said: "I assume that it is possible to define a FEC algorithm that achieves DC balance and has sufficient transitions, but it should not be accepted without analysis."
My point is that this is an obvious failure mode of such a proposal. It should be a possible for you to make a straight-forward logical argument that the particular FEC algorithm that you choose for your proposal (whatever that ends up being) has the property that no single bit in the polynomial output is based solely on the padded bytes. However, in the absence of such an argument, we should not assume that this property holds.
Thanks,
Brian H.
_______________________________________________
Brian Holden PMC-Sierra, Inc.
3975 Freedom Circle, Santa Clara CA USA
+1.408.239.8123 Fax +1.408.492.9462
brian_holden@pmc-sierra.com http://www.pmc-sierra.com
-----Original Message-----
From: Frank Effenberger [mailto:feffenberger@HUAWEI.COM]
Sent: Tuesday, January 16, 2007 4:07 PM
To: STDS-802-3-10GEPON@LISTSERV.IEEE.ORG
Subject: Re: [8023-10GEPON] Example of why doing FEC after scrambling
needs careful analysis
Dear Brian,
As a counter-example of your counter-example, if the FEC code existed where
one of the parity bits depended only on the pad, then we would discard said
parity bit, because it carries zero information content. QED.
Further, even if there exists a parity bit that depends on only one data
bit, since that data bit has been scrambled, the parity bit will also be
scrambled, and hence there is no problem.
In practice, any decent FEC code has the property that each bit in the
parity depends on many bits in the payload. If it doesn't, then the code
error correcting capability will be negatively impacted, because the code
will be devolving to a 'repeat code.' Repeat codes have horrible gain.
Honestly, this is really not a problem. But you are certainly free to
analyze.
Regards,
Frank E.
-----Original Message-----
From: Brian Holden [mailto:Brian_Holden@PMC-SIERRA.COM]
Sent: Tuesday, January 16, 2007 2:34 PM
To: STDS-802-3-10GEPON@listserv.ieee.org
Subject: [8023-10GEPON] Example of why doing FEC after scrambling needs
careful analysis
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All,
During the Q&A after Frank's presentation, I mentioned that it was not
obvious that a FEC's output always has statistical DC balance and sufficient
transitions. This is particularly true given the fact that his proposal
used a RS(255, 239) code, but only used 231 bytes of the input instead of
the full 239.
I thought it would be good to present a simple example which illustrates the
problem case. That example is:
If any given bit of the added FEC parity was based only on the bits
in the unused pad, it would end up with a fixed output value,
independent of any preset value of that pad. This would then break
the DC balance property.
I assume that it is possible to define a FEC algorithm that acheives DC
balance and has sufficient transitions, but it should not be accepted
without analysis.
Alternatively, FEC algorithms exist that have the capability of unwinding
the known, fixed error muliplication caused by operation after a
self-synchronous scrambler.
Brian Holden
_______________________________________________
Brian Holden PMC-Sierra, Inc.
3975 Freedom Circle, Santa Clara CA USA
+1.408.239.8123 Fax +1.408.492.9462
brian_holden@pmc-sierra.com http://www.pmc-sierra.com