RE: CMOS in Serial PMD
I am planning to bring a presentation to the November meeting on these
issues. It must be remembered that we have no mandate to define this
interface. At least not yet. I would recommend that those who believe we
should define this as an ?optional? interface prepare presentations
supporting that position. In short, we should first make it one of our
objectives, or not.
On the other hand, the media side interface for the PMD's has great
diversity and we do have a mandate to define it! This needs to be the focus
of the greater part of our energy. It is here that I would encourage all PMD
advocates to begin to define the optical specifications required to make
their favorite PMD work and interoperate. This would be true for both LAN
and WAN PMDs.
I would recommend each camp bring the following to the November meeting (all
references are from clause 38):
1. a Figure like 38-1
2. tables like 38-2, 38-3, 38-4, 38-5 (with supporting model?), and 38-10
There is less time than you think!
jonathan
> -----Original Message-----
> From: Henning Lysdal [mailto:hl@xxxxxxx]
> Sent: Monday, October 04, 1999 8:54 AM
> To: stds-802-3-hssg@xxxxxxxx
> Subject: CMOS in Serial PMD
>
>
>
> The following questions needs to be answered before
> PMD proposals can be rated against the PHY/PMD
> evaluation criteria:
>
> 1) Somewhere inside a serial PMD the is a N:1 10 or
> 12.5 Gb/s MUX. This requires the N inputs to be
> registered at the same clock (i.e. jitter + skew +
> setup/hold-time < 1 UI, setup+hold-time approx. 150 ps
> in a realistic high speed mux). Since UI = N/LR (LR =
> Line Rate), the skew out of a device driving the N:1
> mux determines the minimum width N. WHAT IS THE
> MINIMUM GUARANTEED SKEW BETWEEN INDIVIDUAL 3.1 Gb/s
> CMOS OUTPUTS?
>
> 2) Assuming the 4 bit serial interface proposed by
> Howard Frazier, all PMD's will contain a CMOS chip for
> management and to take the 4 bit serial into something
> useful to the rest of the PMD (e.g. N:1 MUX/1:N DEMUX
> or jitter clean-up for WDM). HOW MUCH POWER WILL SUCH
> A 4-BIT SERIAL CONVERTER CHIP DISSIPATE?
>
> I hope the answers to the questions above will
> generate new PHY/PMD proposals and alow them to answer
> to the evaluation critiria.
>
> Henning Lysdal
>
>
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