RE: 20 / 100 ppm
Hi all
Just a comment on the 20 / 100 ppm clock accuracy discussion.
As far as I recall from my mind, the 20 ppm (SDH/SONET) spec, is due to the
limited amount of pointer justification. As I understand, the SDH framer can
only adjust +/-8 bit (a byte) pr. two frames (maximum) (the pointer
adjustment is indicated by inverting the even or odd bits of the pointer,
giving a error prone majority decision), so this sets the limitation on
maximum clock difference that the framer can handle before experiencing a
buffer under/overrun.
The situation for 10GE is a little different as one has the idle characters
to insert or delete in order to account for a slight difference in clock
frequencies. THis may be regarded as the equivalent to pointer processing in
SDH framers.
There is normally not any problems with the ref.clk at the RX side. At
least, the GIGA 10 Gb/s CDR devices have a 500 ppm (or 2000 ppm) auto-lock
range detection circuit, which ensures a reliable lock conditions.
Experimentally, I found that the PLL acquisition/capture range is up to
about 20 MHz. This is mainly set by the PLL bandwidth of the CDR, which is
minimum 4 MHz (set by the jitter tolerance criteria). Even when the closed
loop PLL gain drops to 0.1 (at 40 MHz frequency offset) there is still
sufficient gain to pull the VCO into lock.
Benny
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GIGA, an Intel company
Benny Christensen, M.Sc.E.E, Ph.D.
Mileparken 22, DK-2740 Skovlunde, Denmark
Tel: +45 7010 1062, Fax: +45 7010 1063
e-mail: benny.christensen@xxxxxxxxx, http://www.giga.dk
> I have yet to see an explanation as to why a 100 PPM clock
> recovery system
> is more expensive than a 20 PPM clock recovery system. If
> you use the
> argument set by the legacy SONET standards body, the
> receivers for 10GbE
> would be less expensive if the clock were specified at 20
> PPM. I have yet
> to hear from any of the component vendors to support that
> argument. All of
> the component vendors seem to believe that the SONET/SDH version is
> slightly higher in cost.
>