SJTP: WIS Pointer Processor
Ben was correct. The H1H2 pointer value of 522 corresponds to
the POH starting at the top of the SONET frame immediately
after the Z0 byte locations (refer to G.253 figure 3-38).
This alignment changes the proposal I had submitted for the
WIS jitter test pattern in which I had assumed the SPE started
near the middle of the frame. With this new view on alignment,
the impact of the CID pattern is now reflected on the J1 byte.
(Given that a CID can cause transmitter eye closure, or receiver
CDR drift this effect can be measured by the data stream
at the conclusion of the CID).
In order to maintain the effectiveness of CID stress for WIS
compliant PMDs, it will be necessary to program the J1 byte
to a value which has an impact on CID susceptible components.
Fortunately, the J1 byte is already defined to be programmable.
It is now necessary that we fix the value of J1 (just as we
must provide fixed values for all overhead bytes for the pattern
test to be successful).
This benefits the testers since now they can perform two
independent tests from the same pattern. The first being
the CID test with analysis only on the received value of
J1. The second being sensitivity type tests in which the
SNR (etc) is decreased until a BER passes a threshold.
For this type of test the CID is ignored and the PRBS
is the focus.
Several things still have to happen. If there are no exceptions
to this proposed change, I shall update the WIS Jitter Test
Patterns document to reflect the impact of J1. We need input
from PMD people to determine the start pattern for the
PRBS (not all zero), and a value for J1. Finally, all programmable
OH bytes must be asigned a fixed value.
--
Tim Warland P.Eng.
Hardware Design Engineer Broadband Products
High Performance Optical Component Solutions
Nortel Networks (613)765-6634