[RPRWG] RPR Jitter/Delay

[Mike Takefman <tak@xxxxxxxxx>]

Thanks to everyone who chimed in with numbers and
reminded us all that access delay is also a compentent.

As I recall from all of the simulations that had been
done early on in the WG phase that argued about
jitter of 1TQ and 2TQ designs the numbers were always
in the range of 10s of uSeq to 100s of uSeq for a 
ring. 

Bob, was there a specific issue you wanted to raise?


cheers, 

mike

-- 
Michael Takefman              tak@xxxxxxxxx
Manager of Engineering,       Cisco Systems
Chair IEEE 802.17 Stds WG
2000 Innovation Dr, Ottawa, Canada, K2K 3E8
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